This invention relates generally to integrated logic circuits for use on digital communication systems and more particularly, it relates to a transition-based wired "OR" bus circuit which allows interchip communication between numbers of interconnected VLSI (very large scale integration) chips upon a digital bus.
As used herein, wired "OR" logic is defined to mean that any one or ones of all of the interconnected VLSI chips may drive or assert a signal on a common digital bus line while any one or ones of all of the interconnected VLSI chips may receive the asserted signal from the common bus line. There are known heretofore various prior art wired "OR" bus circuits for effecting bused digital communication between interconnected devices. One such prior art wired "OR" bus circuit of FIG. 1 requires the use of an external pull-up resistor R to be connected via a node A to each of the integrated circuit chips 10a, 10b, . . . 10n. In order to effectuate the wired "OR" connection, one or more of the chips may be activated so as to pull-down the node A and thus cause the current to flow through the external resistor R. This scheme has the disadvantages of occupying more space due to this external component, high current drains, and large power dissipation.
Another prior art wired "OR" bus circuit is illustrated in FIG. 2. As can be seen, there is required the use of an external logic gate 12 (i.e., OR gate) in which each of the inputs of the logic gate 12 is connected by a plurality of first conductors 11 to a respective output pin 13 of the integrated circuit chip 14a, 14b, . . . 14n. Further, the output of the logic gate 12 is fed back to each of the integrated circuit chips via a plurality of second conductors 17 and their respective input pin 15. This prior art approach suffers not only from the use of an external component but also from the number of input/output pins needed in the individual integrated circuit chips and associated number of conductors, which imposes severe restraints.
Thus, it would be desirable to provide an improved wired "OR" bus circuit which eliminates the use of any external components and operates with reduced power dissipation. It would also be expedient to provide a wired "OR" bus circuit which utilizes a single signal between all of the integrated circuit chips.